Simulations
REY_LDO_SKY130A
REY_LDO
README.md: “6a30388 Sun Aug 16 19:20:24 2026 +0200 “
REY_LDO: a 1.2 V low-dropout regulator. The reference is a resistive divider from VDD_1V8 (no bandgap), buffered by a two-stage amplifier driving a PMOS pass device; the load range checked is 0 to 200 uA.
Loop stability (lstb)
Loop broken between VDD_1V2 and the feedback input LPI with a Tian probe. Checked at both ends of the load range (Li: no load, Lh: 200 uA).
| Name | Parameter | Description | Min | Typ | Max | Unit | |
|---|---|---|---|---|---|---|---|
| Phase Margin | pm_deg | Spec | 45.000 | 60.000 | 120.000 | ||
| Sch_typ | 23.452 | ||||||
| Sch_etc | 0.404 | 27.600 | 55.516 | ||||
| Gain Margin | gm_db | Spec | -100.000 | -10.000 | -8.000 | dB | |
| Sch_typ | -51.805 | ||||||
| Sch_etc | -99.000 | -15.694 | -0.255 | ||||
| DC loop gain | lf_gain | Spec | 25.000 | 40.000 | 80.000 | dB | |
| Sch_typ | 43.686 | ||||||
| Sch_etc | 21.098 | 49.540 | 62.219 | ||||
| Unity Gain Frequency | ug | Spec | 0.050 | 1.000 | 100.000 | MHz | |
| Sch_typ | 71.035 | ||||||
| Sch_etc | 3.869 | 49.565 | 190.913 | ||||
| Output voltage | v(vdd_1v2) | Spec | 1.1000 | 1.2000 | 1.3000 | V | |
| Sch_typ | 1.1262 | ||||||
| Sch_etc | 0.8747 | 1.1437 | 1.4524 | ||||
| Reference voltage | v(xdut.ref_1v2) | Spec | 1.1000 | 1.2000 | 1.3000 | V | |
| Sch_typ | 1.1992 | ||||||
| Sch_etc | 1.1309 | 1.1973 | 1.2731 |
Transient (tran)
Load step 0 -> 200 uA -> 0 (100 ns edges) and a -100 mV line dip, closed loop. Droop, overshoot, load and line regulation, quiescent current.
| Name | Parameter | Description | Min | Typ | Max | Unit | |
|---|---|---|---|---|---|---|---|
| Output voltage, no load | vout_light | Spec | 1.1000 | 1.2000 | 1.3000 | V | |
| Sch_typ | 1.1568 | ||||||
| Sch_etc | 1.0197 | 1.1377 | 1.4036 | ||||
| Output voltage, 200 uA load | vout_heavy | Spec | 1.0500 | 1.2000 | 1.3000 | V | |
| Sch_typ | 1.1745 | ||||||
| Sch_etc | 0.8747 | 1.1288 | 1.2640 | ||||
| Load step droop (absolute) | vload_min | Spec | 0.9000 | 1.1000 | 1.3000 | V | |
| Sch_typ | -3.9575 | ||||||
| Sch_etc | -7.0407 | -3.2298 | -0.4327 | ||||
| Load release overshoot (absolute) | vload_max | Spec | 1.1000 | 1.2500 | 1.4500 | V | |
| Sch_typ | 1.7319 | ||||||
| Sch_etc | 1.5014 | 1.6838 | 1.8709 | ||||
| Load regulation (0 to 200 uA) | loadreg_v | Spec | -10.000 | 20.000 | 100.000 | mV | |
| Sch_typ | -17.675 | ||||||
| Sch_etc | -100.922 | 12.909 | 263.223 | ||||
| Line regulation (-100 mV step) | linereg_v | Spec | 40.000 | 67.000 | 90.000 | mV | |
| Sch_typ | -31.691 | ||||||
| Sch_etc | -147.176 | 54.822 | 298.344 | ||||
| Quiescent supply current | idd_light | Spec | 2.000 | 20.000 | 60.000 | uA | |
| Sch_typ | 27.684 | ||||||
| Sch_etc | 15.938 | 24.027 | 33.084 |
PSRR (psrr)
1 V AC on VDD_1V8, closed loop; PSRR = db(v(VDD_1V2)) over 10 Hz to 100 MHz, at both load ends.
| Name | Parameter | Description | Min | Typ | Max | Unit | |
|---|---|---|---|---|---|---|---|
| PSRR at DC (10 Hz) | psrr_dc | Spec | -10.000 | -3.500 | -2.000 | dB | |
| Sch_typ | -2.432 | ||||||
| Sch_etc | -17.146 | -2.975 | 20.751 | ||||
| PSRR at 1 kHz | psrr_1k | Spec | -10.000 | -3.500 | -2.000 | dB | |
| Sch_typ | -2.432 | ||||||
| Sch_etc | -17.146 | -2.975 | 20.751 | ||||
| PSRR at 100 kHz | psrr_100k | Spec | -10.000 | -3.500 | -1.000 | dB | |
| Sch_typ | -2.432 | ||||||
| Sch_etc | -17.146 | -2.975 | 20.718 | ||||
| PSRR at 1 MHz | psrr_1meg | Spec | -10.000 | -3.500 | -1.000 | dB | |
| Sch_typ | -2.439 | ||||||
| Sch_etc | -17.168 | -2.982 | 18.191 | ||||
| Worst PSRR (10 Hz to 10 MHz) | psrr_worst | Spec | -10.000 | -2.000 | 1.000 | dB | |
| Sch_typ | -2.432 | ||||||
| Sch_etc | -9.745 | -2.975 | 20.751 |