LELO_TEMP_SKY130A

LELOTEMP_BIAS_IBP

Bandgap core. The voltage across the resistor between VR1 and VD2 will be

\[\Delta V = V_{R1} - V_{D2} = \frac{k T}{q} ln(8 \times 8)\]

since there is a 1-to-8 ratio between the bipolars, and a 1-to-8 ratio in the current mirror.

The current in the resistor will be

\[I_{R} = \frac{\Delta V}{(4 + 8) \times RPPO}\]

Where $RPPO$ is the unit resistor.

The $V_C$ is a bit more complicated, but can be calculated to be

\[V_C = \frac{kT}{q}(\ell - 3 \ln T) + V_G\]

where

\[\ell= \ln{I_D} - \ln{\left (Aq\frac{D_n}{L_n N_A} + \frac{D_p}{L_p N_D}\right)} - 2 \ln{\sqrt{B_c B_v}}\]

where $A$ is the area of the diode, $I_D$ the current in the diode, $D_n,D_p$ are the diffusion constants for electrons and holes. $L_n,L_p$ are the diffusion lengths, $N_A,N_D$ are the acceptor and donor concentration. and $B_c,B_v$ are

\[B_c = 2 \left[\frac{2 \pi k m_n^*}{h^2}\right]^{3/2} \text{ } B_v = 2 \left[\frac{2 \pi k m_p^*}{h^2}\right]^{3/2}\]

where $m_n,m_p$ are the effective mass of electrons and holes and $h$ is Planck’s constant.

Obviously.

Not really.

But it is understandable.

See Diodes

Estimated values from the model in LELO_TEMP.py are shown in table below.

Temperature [C] Current [uA] Vc [V] DeltaV [mV]
-40 0.902 0.8386 83.6
25 1.133 0.7412 106.9
125 1.425 0.5844 142.7

The diode connected transistor on the right side is to clamp the voltage between VR1 and VD2. If the current is too high, then a high voltage on VR1 can turn off the PMOS in the OTA, and increase settling time.

LELOTEMP_OTAR

Current mirror OTA, and the amplifier that closes the bandgap loop. It is the same circuit idea as LELOTEMP_OTA, rebuilt from the REY_ATR library. The name changed because the cells did, not because the function did.

The inputs sit across the two bandgap branches, $V_{R1}$ on VIP and $V_{D1}$ on VIN, and the output LPO drives the gates of the PMOS current mirror. The loop settles when the OTA has forced the two branches to the same voltage, which is what makes $\Delta V$ appear across the resistor between VR1 and VD2.

The bias is a resistor from the tail of the differential pair to VDD, not a current from the bandgap. Same reason as in the other OTAs: taking the bias from the loop the OTA is closing complicates startup, and the point of a resistor here is that the OTA keeps working before the bandgap does. The tail resistor is four segments of high sheet poly in series, so

\[I_{TAIL} = \frac{V_{DD} - V_{S}}{4 R_{PPO}}\]

where $V_S$ is the source of the input pair, one $V_{SG}$ above the input common mode.

The input pair is low threshold PMOS. The inputs are a diode voltage above VSS and the sources are near VDD, so at the low supply corner the $V_{SG}$ the pair needs is a large fraction of what the supply has left after the tail resistor drop. The LVT devices buy that headroom back. This is the part of the circuit that the 1.7 V corner leans on hardest.

Both branches are loaded with diode connected NMOS, and the two branch voltages are then mirrored into the output stage: VD1 drives an NMOS into the diode connected PMOS at VBP, and VD2 drives an NMOS at VO against the PMOS mirrored from VBP. The gain is therefore taken in the second stage rather than at the drains of the input pair.

The output is pulled high in power down, so that the PMOS current mirror in the bandgap is turned off. VD1, VD2 and VD3 are pulled to VSS, and the tail switch between VDD and the resistor is opened, so no current flows.

The circuit on the right side generates the VCP cascode bias for the main bandgap, from a replica input pair into a diode connected NMOS at VD3 and a series PMOS string down from VDD.

LELO_TEMP

Bandgap (LELOTEMP_BIAS_IBP) is used to provide a PTAT current for the frequency conversion and the comparator. The $V_C$ is the CTAT diode voltage in the bandgap. The output current is approximately 1 uA.

The current charges the capacitor inside CCMPR. When the voltage on the capacitor reaches $V_C$ the comparator inside CCMPR will trigger (low to high).

The two comparators alternate to trigger the set/reset latch made by the NOR gates. As such, the two capacitors are alternatively charged.

The output frequency can be calculated from the voltage/current relationship of a capacitor.

A single charge cycle is given by

\[I = C \frac{dV}{dt} \Rightarrow dt = C \frac{V_C}{I}\]

Inserting for the bandgap current ($I_R$)

\[dt = RC \frac{V_C}{\Delta V}\]

As such, the frequency will be

\[f_{OSC} = \frac{1}{2 dt} = \frac{1}{2RC} \frac{\Delta V}{V_C}\]

The $\Delta V$ increases with temperature and $V_C$ decreases with temperature, turns out the $\Delta V$ increases faster than $V_C$ drops, so the overall gradient is positive.

The estimated frequency is shown in the table below (computed by the calibrated extracted-view model in LELO_TEMP.py)

Temperature [C] Frequency [MHz]
-40 1.399
25 1.994
125 3.185

LELOTEMP_CCMPR

The timing element of the oscillator. One 1U current from the bandgap charges a capacitor, and LELOTEMP_CMPR triggers when the capacitor reaches $V_C$. Two of these alternate through the set/reset latch in LELO_TEMP, so each one produces half a period.

The bias input IBP_1U<0> is also the integrating node. There is no separate input pin for the ramp: the current arrives on the same wire that the capacitors and the comparator input hang on. IBP_1U<1> is the comparator’s own bias.

The capacitor is five MIM unit cells. The NMOS gated by RST discharges the node between cycles, and a second NMOS gated by PWRUP_N holds it down in power down, so the oscillator starts from a known state rather than from whatever charge was left on the plate.

The half period follows from the capacitor relationship,

\[dt = C \frac{V_C}{I}\]

but the comparator does not switch at the instant the ramp reaches $V_C$. Its delay $t_d$ lets the ramp continue past the threshold, and that adds to every half period,

\[t_{HALF} = C \frac{V_C}{I} + t_d\]

so a delay that drifts over temperature is a temperature error, not a second order effect.

The integrating node also carries the bandgap-to-pair distribution wire, which crosses the whole tile, so $C$ is more than the five unit cells: the effective capacitance fitted from the typical top-level runs is 319 fF (Sch) and 385 fF (Lay) – see FIT in LELO_TEMP.py.

LELOTEMP_CMPR

A two-stage OTA used as comparator. Uses a 1U bias current from the bandgap.

It also owns the ramp node housekeeping: an NMOS gated by RST discharges the integrating node between cycles, and one gated by PWRUP_N holds it down in power down.

TB_LELO_TEMP

A top level debug testbench for the temperature sensor. If you open the testbench in Xschem you’ll see there are waveforms to view signals inside the temperature sensor.

A debug testbench like this is quite useful to figure out what’s going on, and see what voltages and currents are present in the design.