Command

cicsim --no-color portreplace --help

Usage: cicsim portreplace [OPTIONS] TESTBENCH SOURCE CELL

  Replace ${PORTS} and ${VPORTS} with the subcircuit ports of SOURCE CELL

Options:
  --help  Show this message and exit.

Description

portreplace is a utility that reads a SPICE subcircuit definition and replaces port placeholders in a testbench file.

This is useful when you want a testbench to automatically adapt to the ports of the device under test, without manually listing them.

Usage

cicsim portreplace TESTBENCH SOURCE CELL

Where:

  • TESTBENCH is the SPICE file to modify (edited in-place)
  • SOURCE is the SPICE file containing the subcircuit definition
  • CELL is the name of the subcircuit to extract ports from

Placeholders

The command looks for two placeholders in the testbench:

Placeholder Replaced with
${PORTS} Space-separated list of port names
${VPORTS} Space-separated list of v(port) voltage probes

Example

Given a subcircuit in netlist.spice:

.SUBCKT MY_AMP INP INN OUT VDD VSS
...
.ENDS

And a testbench tran.spi:

XDUT ${PORTS} MY_AMP
.save ${VPORTS}

Running:

cicsim portreplace tran.spi netlist.spice MY_AMP

Will modify tran.spi to:

XDUT INP INN OUT VDD VSS MY_AMP
.save v(INP) v(INN) v(OUT) v(VDD) v(VSS)