Digital to analog conversion
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Processing of signals has shifted into the digital domain. But the real world is analog. In order to interact with the analog we need to convert the digital signals (discrete-value, discrete-time) back to analog signals (continuous value, continuous time).
The SI base units define the fundamental analog quantities as second, meter, kilogram, ampere, kelvin, mole and candela (</aic2026/a_refresher>). Assume that electronic circuits interact with the real world in terms of second and ampere.
Related to Ampere we have the derived units of charge (Ampere Seconds), Volt (W/A), Ohm (V/A), or indeed Simens (1/$\Omega$).

As such, to create a digital to analog converter, we somehow have to create a circuit that has a function of
\[I_{out} = D_{in} \times I_{ref}\text{ [I]}\] \[t_{out} = D_{in} \times t_{ref}\text{ [s]}\] \[Q_{out} = D_{in} \times Q_{ref}\text{ [C]}\] \[V_{out} = D_{in} \times V_{ref}\text{ [V]}\] \[R_{out} = D_{in} \times R_{ref}\text{ [}\Omega\text{]}\]The digital value is dimensionless, as such, there must be a reference value
Digital to analog conversion can be indirect through the relations between voltage, resistance, current, time, inductance and capacitance.
\[V = R I\] \[Q = C V\] \[dt = \frac{C dV}{I}\] \[dt = \frac{L dI}{V}\]Resistor based DACs
DAC errors
Digital to analog converters do not add quantization error. The quantization error is already in the digital word.
\[V_{out} = a_1^1 D_{in}^1 + B + \left( a_n^n D_{in}^n + ... a_2^2 D_{in}^2\right)\]DAC output will contain gain errors, offset errors, and non-linear components
DAC complexity
As number of resistors grow, the switches grow as
\[\sum_{n=1}^{N} 2^n = 2^{N+1} - 2\]Use a matrix with R rows and C columns. Need R + C switches, or
\[2^{N} + 2^{N/2}\]Switches in a 10-bit digital to analog converter.
\[\begin{array}{ll} \text{Tree: } &2^{N+1}-2 = 2046 \\ \text{Matrix : } &2^{N} + 2^{N/2} = 1056 \\ \text{6b Matrix + 4b Tree: } & 2^{M+1} - 2 + 2^{N} + 2^{N/2} = 80 \end{array}\]Large number of bits, will be large number of resistors and switches.
Binary scaled DACs
\[R_{in} = 2R || 2R = R\]Binary coding
For 4 states (2-bit) there are 12 possible transitions
Assume MSB first (left)
\[1 \rightarrow 3 \rightarrow 2\]Assume LSB first (right)
\[1 \rightarrow 0 \rightarrow 2\]Both cause a non-monotonic glitch during transition.
Thermometer encoding
The sequence of MSB to LSB does not matter.
\[0 \rightarrow 1 \rightarrow 2 \rightarrow 3\]Current mode DACs
References
A 10-bit Charge-Redistribution ADC Consuming 1.9 uW at 1 MS/s
A 6.3 uW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 uV Offset
A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With >70 dB SFDR up to 500 MHz