SUN_PLL_SKY130NM

SUN_PLL

For a full description of PLL’s see AIC2024 PLL lecture.

A PLL can consist of a oscillator (SUN_PLL_ROSC) that generates our output frequency. A divider (SUN_PLL_DIVN) that generates a feedback frequency that we can compare to the reference. A Phase and Frequency Detector (SUN_PLL_PFD) and a charge-pump (SUN_PLL_CP) that model the $+$, or the comparison function in our previous picture. And a loop filter (SUN_PLL_LPF and SUN_PLL_BUF).

SUN_PLL_BIAS

So a single NMOS used to generate a bias voltage like this is a dangerous design. You should really distribute bias currents.

I know what I’m doing, and I know that I have to make sure that all NMOS have IBPSR_1U as a gate volage needs to have the same ground as my bias transistor.

It’s also important that the bias transistor has the same current direction as the others.

SUN_PLL_BUF

Low dropout regulator to drive the ring-oscillator. I need a voltage buffer after the low pass filter, since the low pass filter cannot supply ring-oscillator current.

SUN_PLL_CP

Direct a bias current to LPF depending on the CP_UP and CP_DOWN signals. The KICK is to try and speedup the startup of the PLL._

SUN_PLL_DIVN

D-flip-flop ripple counter to divide the oscillator output frequency by 32

SUN_PLL_KICK

Generate a kick pulse using a edge trigger.

There is an inverting delay from PWRUP_1V8_N to N7.

A NOR has the truth table

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

As such, we’ll get the following sequence

Event PWRUP_1V8 PWRUP_1V8_N N7 KICK
0 0 1 0 0
1 1 0 0 1
2 1 0 1 0

And the KICK will go high for a short while when PWRUP_1V8 goes high._

SUN_PLL_LPF

Type-II compensation

SUN_PLL_PFD

Phase detector based on TSPC flip flops.

To analyise circuits like this you need to make some assumptions.

Let’s assume that CP_DUP_N = 0 and CP_DOWN_N = 0.

We know that ideally CK_REF and CK_FB should be the same frequency.

Let’s first check what happens when frequency of CK_REF > CK_FB

As we can see, the UP signal is mostly high, and the DOWN signal is mostly low. As such, the charge pump will inject current into the low pass filter and increase the VCO frequency

When CK_REF < CK_FB, then

As we can see, the DOWN signal is mostly high, and UP signal is mostly low. As such, the charge pump will pull current from the low pass filter and reduce the VCO frequency

SUN_PLL_ROSC

This is a BAD ring oscillator. It’s bad because it has a high VCO gain (large change in frequency for a small change in oscillator voltage).

You should use a better one.

The ring oscillator core runs on the buffered low pass filter voltage. To ensure full scale for the output clock I use a level shifter

SUN_PLL_LSCORE

Standard level shifter.