Slides

TFE4152 - Lecture 4

MOSFET’s

Source

Goal for today

  • Symbols
  • Current characteristics
  • Operating regions
  • The square-law model
  • Channel length modulation
  • The small signal model (low frequency)
  • Bulk Effect

Metal-Oxide-Semiconductor (MOS) Transistors

NMOS conduct for positive gate-to-source voltage

PMOS conduct for negative gate-to-source voltage

Drain Source Current (\(I_{DS}\))

dicex/sim/spice/NCHIO

Large signal model

\(I_{DS} = f(V_{GS},V_{DS},...)\)

Gate Source Voltage (\(V_{GS}\))

dicex/sim/spice/vgate.cir:


.include ../../../lib/SUN_TRIO_GF130N.spi
.include ../../../models/ptm_130.spi

vdrain  D  0  dc  1
vgate   G  0  dc  0.5

vbulk   B  0  dc  0
vcur    S  0  dc  0

X1 D G S B NCHIO

.dc vgate 0 1.8 0.01

.plot I(vcur)

dicex/lib/SUN_TRIO_GF13N.spi:

.SUBCKT NCHIO D G S B
M1   D   G   S   B  nmos   w=1.08u    l=0.6u
.ENDS

dicex/models/ptm_130.spi

.model  nmos  nmos  level = 21
+version = 4.0          binunit = 1            paramchk= 1            mobmod  = 0
+capmod  = 2            igcmod  = 1            igbmod  = 1            geomod  = 1
+diomod  = 1            rdsmod  = 0            rbodymod= 1            rgatemod= 1
+permod  = 1            acnqsmod= 0            trnqsmod= 0

+tnom    = 27           toxe    = 2.25e-9      toxp    = 1.6e-9       toxm    = 2.25e-9
+dtox    = 0.65e-9      epsrox  = 3.9          wint    = 5e-009       lint    = 10.5e-009
...(about 60 more lines)

Gate-source voltage

Param Voltage [V]
VGS 0 to 1.8
VDS 1.0
VS 0
VB 0
\[i(vcur) = I_{DS}\]

Inversion level

Define \(V_{eff} \equiv V_{GS} - V_{tn}\), where \(V_{tn}\) is the “threshold voltage”

Veff Inversion level
< 0 weak inversion or subthreshold
0 moderate inversion
> 100 mV strong inversion

Weak inversion

The drain current is low, but not zero, when \(V_{eff} << 0\)

\[I_{DS} \approx I_{D0} \frac{W}{L} e^{V_{eff}/n V_{T}} \text{ if } V_{DS} > 3 V_{T}\] \[n \approx 1.5\]

Moderate inversion

Stay away from moderate inversion for analog design.

If you can’t, then trust the model

Strong inversion

\[I_{DS} = \mu_n C_{ox} \frac{W}{L} \begin{cases} V_{eff} V_{DS} & \text{if }V_{DS} << V_{eff} \\[15pt] V_{eff} V_{DS} - V_{DS}^2/2 & \text{if } V_{DS} < V_{eff} \\[15pt] \frac{1}{2} V_{eff}^2 & \text{if } V_{DS} > V_{eff} \\[15pt] \end{cases}\]

The threshold voltage (\(V_{tn}\)) is defined as \(p_p = n_{ch}\)

Gate Source Capacitance (\(C_{GS}\))

\(C_{GS} \text{ for } V_{DS} = 0, V_{S} = 0\)

In strong inversion

\[C_{GS} = W L C_{ox}\]

where

\[C_{ox} = \frac{K_{ox} \epsilon_0}{t_{ox}}\] \[Q_{ch} = W L C_{ox} V_{eff}\]

Drain Source Voltage (\(V_{DS}\))

Drain-source voltage

Param Voltage [V]
VGS 0.5
VDS 0 to 1.8
VS 0
VB 0
\[i(vcur) = I_{DS}\]

Strong inversion

\[I_{DS} = \mu_n C_{ox} \frac{W}{L} \begin{cases} V_{eff} V_{DS} & \text{if }V_{DS} << V_{eff} \\[15pt] V_{eff} V_{DS} - V_{DS}^2/2 & \text{if } V_{DS} < V_{eff} \\[15pt] \frac{1}{2} V_{eff}^2 & \text{if } V_{DS} > V_{eff} \\[15pt] \end{cases}\]

Head simulation

Channel length modulation

\[I_{DS} = \mu_n C_{ox} \frac{W}{L} \begin{cases} V_{eff} V_{DS} & \text{if }V_{DS} << V_{eff} \\[15pt] V_{eff} V_{DS} - V_{DS}^2/2 & \text{if } V_{DS} < V_{eff} \\[15pt] \frac{1}{2} V_{eff}^2[1 + \lambda(V_{DS} - V_{eff})] & \text{if } V_{DS} > V_{eff} \\[15pt] \end{cases}\]

\(\lambda = \frac{k_{ds}}{2L\sqrt{V_{DS} - V_{eff} + \Phi_0}}\), where \(k_{ds} = \sqrt{\frac{2K_s \epsilon_0}{q N_A}}\)