How should I size my transistor

• From the book?
• The best method (as of today)
• Not connected info, but still cool

One of the more common questions asked by students is “How should I size my transistor?”. There is no simple answer to that question. As many things in life, it’s complicated.

From the book?

In the books we learn the equations for weak inversion

\[I_D \propto (e^{(V_{gs}-V_{th})/U_T}-1)\]

, where $I_D$ is the drain current, $V_{gs}$ is the gate source voltage, $V_{th}$ is the threshold voltage and $U_T = kT/q$, where $k$ is Boltzmann’s constant, $T$ is the temperature in Kelvin and $q$ is the unit charge

The equation is similar to bipolar and diode equations, because the physics is the same.

The drain current in weak inversion is mostly a diffusion current and relates to the density of electrons in the conduction band (for an NMOS), which can be computed from the density of available energy states, and the Fermi-Dirac distribution.

\[n = \int_{E_C}^{\infty}N(E)\frac{1}{e^{(E-E_F)/kT}+1}dE\]

, where $n$ is the density of electrons in the conduction band, $N(E)$ is the density of available energy states, $E$ is the integration variable (and the energy) and $E_F$ is the Fermi-level.

Maybe the equation looks complicated, but it’s really “Multiply the available energy state with the probability of being in that state, and sum for all available energy states”.

Changing the voltage changes the number of free electrons, simply because we bring the conduction band closer to the Fermi level.

The Fermi level is just something we invented, and just means “If there was an quantum state at the Fermi level Energy, then it would have a 50 % probability of being occupied by a electron”.

In the equation above, moving the conduction band edge is equivalent to reducing the $E_C$. As such, more of the Fermi-Dirac distribution has available energy states $N(E)$, and the density of electrons $n$ in conduction band becomes higher.

In strong inversion, the MOSFET is more like a voltage controlled resistor with a conductance that is proportional to gate-source voltage.

The density of electrons increases because we bend the conduction band beyond the Fermi level, as a result, most of the available energy states in the conduction band are filled by electrons. Electrons are only free to move, however, close to the surface of the silicon, as far away from the surface, we don’t feel the effects of the gate voltage, and the conduction band stays at the same energy. As a result, electrons form a 2 dimensional electron gas close to the silicon surface. What we call an inversion layer.

The threshold voltage is defined as the point when the density of electrons in the inversion layer is equal to the density of holes in the substrate, or bulk, which usually is a p-type semiconductor for an NMOS.

Once we have that electron gas, or inversion layer, we have a connection between the drain and source n-type regions, and the current can be estimated by a drift current. The diffusion current will still be there, but much smaller magnitude than the drift current, so we drop the diffusion current, and get

\[I_D = \frac{1}{2} \mu_n C_{ox}\frac{W}{L}(V_{gs}-V_{th})^2\]

The equations in the books are good to give a physical understanding of what happens. Although, we tend to forget that everybody forgets.

We teach quantum physics one year, and how to compute the density of states $N(E)$ from Schrodinger, the wave-function and Fermi-Dirac distribution.

Next year we talk about semiconductors, crystal lattice, band structure (density of states as a function of space), energy diagrams (band structure is complex, so we just use the lowest conduction band and highest valence band), doping to shift the Fermi level, and how we can create PN-junctions, bipolars and MOSFETS.

The year after we teach the current equations for MOSFETs, and the books don’t have the link back to solid-state physics, after all, we already told the students that, they should remember!

I think, quite often, we just end up with confused students. And I don’t think it’s necessary to end up with confused students. Maybe sometimes we end up with confused students because the Professors can’t necessarily remember where the equations come from either, nor how electrons and holes really behave.

It’s not necessary for an analog design student to remember how to compute the density of available energy states from Schrodinger and the wave function. If we wanted to use the relativistc version of Schrodinger (which includes magnetic fields, and if you did not know, magnetic fields is just a relativistic effect of the electric field) and the wave function to compute how an Silicon atom actually behaves, I don’t think we can. As far as I’ve been able to figure out, it’s not possible to have a closed form solution (symbolic), nor is it possible with supercomputers to do a numeric time-evolution of the states in a single Silicon atom with all the inter-particle interactions, space, momentum, spins, electric fields and magnetic fields.

But we can make sure we connect the links from Schrodinger to the MOSFET equations, that’s easy, that’s what I’ve tried to do in the previous section.

For answering the question “How should I size my transistor?”, the above section does not really give an answer, they serve as the basis for the answers, but not the actual answer.

The best method (as of today)

The method that makes most sense to me, is to use the inversion-coefficient method, described in Nanoscale MOSFET Modeling: Part 1 and Nanoscale MOSFET Modeling: Part 2.

The inversion coefficient tells us how strongly inverted the MOSFET channel (inversion layer) is. A number below 0.1 is weak inversion, between 0.1 and 10 is moderate inversion. A number above 10 is strong inversion.

There are also some blog posts worth looking at Inversion Coefficient Based Circuit Design and My Circuit Design Methodology.

I should caveat my proposal for method. For the past 7 years I’ve not had the luxury to do full time, hardcore, analog design. As my career progressed, most of my time is now spent telling others what I think is a good idea to do, and not doing hardcore analog design myself. I think, however, I have a pretty decent understanding of analog circuits, and how to design them, so I think I’m correct in the proposal. If I were to start hardcore analog design now, I would go all in on inversion-coefficient based transistor size selection.

Maybe next holiday I’ll have time to characterize Skywater 130 nm for analog design using the inversion coefficient method above. Or maybe you will beat me to it, and do it for me. That’s even better, because if you publish it, then I can just use whatever you found out.

Not connected info, but still cool

I’ve been programming since 1999, and alot has happened in the world of software since then. This post was written on my iPad Air with a magic keyboard, using vscode.dev, writing in Markdown, committing and pushing directly to github.com/wulffern/aic2023, which uses a github action to build a Jekyll site that is automatically pushed to wulffern.github.io/aic2023/mossize. For a lazy person like me, it’s fantastic how we have progressed. I can now spend all my effort on the content, and the rest is automated!