MOSFETs

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Metal Oxide Semiconductor

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Field Effect

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Analog transistors in the books

In the books we learn the equations for weak inversion

I_D \propto e^{(V_{gs}-V_{tn})/nV_T}

In strong inversion, the MOSFET is more like a voltage controlled resistor with a conductance that is proportional to gate-source voltage.

I_D = \frac{1}{2} \mu_n C_{ox}\frac{W}{L}(V_{gs}-V_{tn})^2

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Transistors in weak inversion

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I_{D} = I_{D0} \frac{W}{L} e^{q(V_{GS} - V_{tn})/ n kT}

where

n = (C_{ox} + C_{j0})/C_{ox}

I_{D0} = (n - 1) \mu_n C_{ox} \left(\frac{kT}{q}\right)^2

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g_m = \frac{I_D}{nV_T}

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Transistors in strong inversion

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Carrier transport near the Si/SiO2 interface of a MOSFET

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Introduction to behavior

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Let's assume we know nothing about how transistors work, but we do know how to simulate them in ngspice.

We could sit down, and try and figure out how the transistors work.

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Drain Source Current

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I_{DS} = f(V_{GS},V_{DS},...)

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Gate Source Voltage

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Gate-source voltage

Param	Voltage
VGS	0 to 1.8
VDS	1.0
VS	0
VB	0

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Inversion level

Define \(V_{eff} \equiv V_{GS} - V_{tn}\) , where \(V_{tn}\) is the "threshold voltage"

Veff	Inversion level
less than 0	weak inversion or subthreshold
0	moderate inversion
more than 100 mV	strong inversion

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Weak inversion

The drain current is low, but not zero, when

V_{eff} << 0

I_{DS} \approx I_{D0} \frac{W}{L} e^{V_{eff}/n V_{T}} \text{ if } V_{DS} > 3 V_{T}

n \approx 1.5

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Moderate inversion

Very useful region in real designs. Hard for hand-calculation. Trust the model.

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Strong inversion

I_{DS} = \mu_n C_{ox} \frac{W}{L} \begin{cases} V_{eff} V_{DS} & \text{if }V_{DS} << V_{eff} \\[15pt] V_{eff} V_{DS} - V_{DS}^2/2 & \text{if } V_{DS} < V_{eff} \\[15pt] \frac{1}{2} V_{eff}^2 & \text{if } V_{DS} > V_{eff} \\[15pt] \end{cases}

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The threshold voltage (\(V_{tn}\)) is defined as \(p_p = n_{ch}\)

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Drain source voltage

Param	Voltage [V]
V_GS	0.5
V_DS	0 to 1.8
V_S	0
V_B	0

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Strong inversion

I_{DS} = \mu_n C_{ox} \frac{W}{L} \begin{cases} V_{eff} V_{DS} & \text{if }V_{DS} << V_{eff} \\[15pt] V_{eff} V_{DS} - V_{DS}^2/2 & \text{if } V_{DS} < V_{eff} \\[15pt] \frac{1}{2} V_{eff}^2 & \text{if } V_{DS} > V_{eff} \\[15pt] \end{cases}

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Low frequency model

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g_{m} = \frac{\partial I_{DS}}{\partial V_{GS}}

g_{ds} = \frac{1}{r_{ds}} = \frac{\partial I_{DS}}{\partial V_{DS}}

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Transconductance

Define \(\ell = \mu_n C_{ox} \frac{W}{L}\) and \(V_{eff} = V_{GS} - V_{tn}\)

\(I_{D} = \frac{1}{2} \ell (V_{eff})^2\) and \(V_{eff} = \sqrt{\frac{2I_{D}}{\ell}}\) and \(\ell = \frac{2I_D}{V_{eff}^2}\)

g_m = \frac{ \partial I_{DS}} {\partial V_{GS}} = \ell V_{eff} = \sqrt{2 \ell I_{D}}

g_m = \ell V_{eff} = 2 \frac{I_D}{V_{eff}^2} V_{eff} = \frac{2 I_D}{V_{eff}}

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Define \(\ell = \mu_n C_{ox} \frac{W}{L}\) and \(V_{eff} = V_{GS} - V_{tn}\)

\(I_D = \frac{1}{2} \ell V_{eff}^2\left[1 + \lambda (V_{DS} - V_{eff})\right]\)

\frac{1}{r_{ds}} = g_{ds} = \frac{ \partial I_D}{\partial V_{DS} } = \lambda \frac{1}{2} \ell V_{eff}^2

Assume channel length modulation is not there, then

\(I_D = \frac{1}{2} \ell V_{eff}^2\) which means \(\frac{1}{r_{ds}} = g_{ds} \approx \lambda I_D\)

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Intrinsic gain

Define intrinsic gain as

A = \left\vert \frac{v_{out}}{v_{in}}\right\vert = g_m r_{ds} = \frac{g_m}{g_{ds}}

A = \frac{2 I_D}{V_{eff}} \times \frac{1}{ \lambda I_D } = \frac{2}{\lambda V_{eff}}

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Body effect

V_{tn} = V_{t0} + \gamma\left(\sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F}\right)

\gamma = \frac{\sqrt{2 q N_A \epsilon_{si}}}{C_{ox}}

g_{s} = \frac{\partial I_{DS}}{\partial V_{SB}} \approx (n - 1) g_m \approx 0.2 g_m

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High frequency model

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\(C_{gs}\) and \(C_{gd}\)

C_{gs} = \begin{cases} WLC_{ox} & \text{if }V_{DS} = 0 \\[15pt] \frac{2}{3}WLC_{ox} & \text{if }V_{DS} > V_{eff} \\[15pt] \end{cases}

C_{gd} = C_{ox} W L_{ov}

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\(C_{sb}\) and \(C_{db}\)

Both are depletion capacitances

C_{sb} = (A_s + A_{ch}) C_{js}

C_{js} = \frac{C_{j0}}{\sqrt{1 + \frac{V_{SB}}{\Phi_0}}}

\Phi_0 = V_T ln\left(\frac{N_A N_D}{n_i^2}\right)

C_{db} = A_d C_{jd}

C_{jd} = \frac{C_{j0}}{\sqrt{1 + \frac{V_{DB}}{\Phi_0}}}

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Be careful with Cgd (blame Miller)

If \(Y(s) = 1/sC\) then \(Y_1(s) = 1/sC_{in}\) and \(Y_2(s) = 1/sC_{out}\) where \(C_{in} = (1 + A) C\), \(C_{out} = (1 + \frac{1}{A})C\)

C_{in} \approx C_{gd}\, g_{m} r_{ds}

\(C_{gd}\) can appear to be 10 to 100 times larger!

if gain from input to output is large

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Transit frequency

f_T = \frac{g_m}{2 \pi (C_{gs} + C_{gd})}

In strong inversion, with \(C_{gs} \approx \frac{2}{3} W L C_{ox}\):

f_T \approx \frac{3 \mu_n V_{eff}}{4 \pi L^2} \propto \frac{V_{eff}}{L^2}

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Weak inversion

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If \(V_{eff} < 0\) diffusion currents dominate.

\(I_{D} = I_{D0} \frac{W}{L} e^{V_{eff} / n V_T}\), where

\(V_T = kT/q\), \(n = (C_{ox} + C_{j0})/C_{ox}\)

I_{D0} = (n - 1) \mu_n C_{ox} V_T^2

g_m = \frac{I_D}{nV_T}

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Bang for the buck

Subthreshold:

\(\frac{g_m}{I_D} = \frac{1}{nV_T} \approx 25.6 \text{ [S/A] @ 300 K}\)

Strong inversion:

\(\frac{g_m}{I_D} = \frac{2}{V_{eff}}\)

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Velocity saturation

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Electron speed limit in silicon

v \approx 10^7 cm/s

v = \mu_n E = \mu_n \frac{dV}{dx}

\(\mu_n \approx 100 \text{ to } 600 \text{ } cm^2/Vs\) in nanoscale CMOS

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Square law model

\(Q(x) = C_{ox}\left[V_{eff} - V(x)\right]\)

\(v = \mu_n E = \mu_n \frac{dV}{dx}\)

\ell = \mu_n C_{ox} \frac{W}{L}

I_{D} = W Q(x) v = \ell L \left[ V_{eff} - V(x)\right] \frac{dV}{dx}

I_{D} dx = \ell L \left[ V_{eff} - V(x)\right] dV

I_{D} \int_0^L{dx} = \ell L \int_0^{V_{DS}}{\left[ V_{eff} - V(x)\right] dV}

I_{D} \left[x\right]_0^L = \ell L \left[V_{eff}V - \frac{1}{2}V^2\right]_0^{V_{DS}}

I_{D} L = \ell L \left[V_{eff}V_{DS} - \frac{1}{2} V_{DS}^2\right]

@ V_{DS} = V_{eff} \Rightarrow I_{D} = \frac{1}{2} \ell V_{eff}^2

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Mobility Degradation

Multiple effects degrade mobility

Velocity saturation
Vertical fields reduce channel depth => more charge-carrier scattering

\ell = \mu_n C_{ox} \frac{W}{L}

\mu_{n\_eff} = \frac{\mu_n}{([1 + (\theta V_{eff})^m])^{1/m}}

I_{D} = \frac{1}{2} \ell V_{eff}^2 \frac{1}{([1 + (\theta V_{eff})^m])^{1/m}}

From square law \(g_{m} = \frac{\partial I_{D}}{\partial V_{GS}} = \ell V_{eff}\)

With mobility degradation \(g_{m(mob-deg)} = \frac{\ell}{2 \theta}\)

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What about holes (PMOS)

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In PMOS holes are the charge-carrier (electron movement in valence band)

\mu_p < \mu_n

In intrinsic silicon: \(\mu_n \leq 1400 [cm^2/Vs] = 0.14 [m^2/Vs]\) \(\mu_p \leq 450 [cm^2/Vs] = 0.045 [m^2/Vs]\)

\mu_n \approx 3\mu_p

Saturation velocity (same as the electron speed limit above):

\(v_{n\_sat} \approx 1.0 \times 10^5 [m/s]\) \(v_{p\_sat} \approx 0.8 \times 10^5 [m/s]\)

_{Don't confuse it with the thermal velocity \(\approx 2.3 \times 10^5\) m/s}

Doping (\(N_A \text{ or } N_D\)) reduces \(\mu\)

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OTHER

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As we make transistors smaller, we find new effects that matter, and that must be modeled.

_{which is an opportunity for engineers to come up with cool names}

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Analog Circuit Design in Nanoscale CMOS Technologies [@lewyn09] -- ieeexplore.ieee.org/document/5247174

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Drain induced barrier lowering (DIBL)

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Well Proximity Effect (WPE)

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Stress effects

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Stress	PMOS	NMOS
Stretch Fz	Good	Good
Compress Fy	OK	Good
Compress Fx	Good	Bad

What can change stress?

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Gate current

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Hot carrier injection

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Channel initiated secondary-electron (CHISEL)

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Variability

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Provide \(I_2 = 1 \mu A\)

Let's use off-chip resistor \(R\), and pick \(R\) such that \(I_1 = 1 \mu A\)

Use \(\frac{W_1}{L_1} = \frac{W_2}{L_2}\)

What makes \(I_2 \ne 1 \mu A\)?

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Voltage variation
Systematic variations
Process variations
Temperature variation
Random variations
Noise

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Voltage variation

I_1 = \frac{V_{DD} - V_{GS1}}{R}

If \(V_{DD}\) changes, then current changes.

Fix: Keep \(V_{DD}\) constant

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Systematic variations

If \(V_{DS1} \ne V_{DS2} \rightarrow I_1 \ne I_2\)

If layout direction of \(M_1 \ne M_2 \rightarrow I_1 \ne I_2\)

If current direction of \(M_1 \ne M_2 \rightarrow I_1 \ne I_2\)

If \(V_{S1} \ne V_{S2} \rightarrow I_1 \ne I_2\)

If \(V_{B1} \ne V_{B2} \rightarrow I_1 \ne I_2\)

If \(WPE_{1} \ne WPE_{2} \rightarrow I_1 \ne I_2\)

If \(Stress_{1} \ne Stress_{2} \rightarrow I_1 \ne I_2\) ...

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Process variations

Assume strong inversion and active \(V_{eff} = \sqrt{\frac{2}{\mu_p C_{ox} \frac{W}{L}} I_1}\), \(V_{GS} = V_{eff} + V_{tp}\)

\(I_1 = \frac{V_{DD} - V_{GS}}{R} = \frac{V_{DD} - \sqrt{\frac{2}{\mu_p C_{ox} \frac{W}{L}} I_1} - V_{tp}}{R}\)

\(\mu_p\), \(C_{ox}\), \(V_{tp}\) will all vary from die to die, and wafer lot to wafer lot.

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Process corners

Common to use 5 corners, or Monte-Carlo process simulation

Corner	NMOS	PMOS
Mtt	Typical	Typical
Mss	Slow	Slow
Mff	Fast	Fast
Msf	Slowish	Fastish
Mfs	Fastish	Slowish

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Fix process variation

Use calibration: measure error, tune circuit to fix error

For every single chip, measure voltage across known resistor \(R_1\) and tune \(R_{var}\) such that we get \(I_1 = 1 \mu A\)

Be careful with multimeters, they have finite input resistance (typically 10 M\(\Omega\))

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Temperature variation

Mobility decreases with temperature

Threshold voltage decreases with temperature.

I_D = \frac{1}{2}\mu_n C_{ox} \frac{W}{L} (V_{GS} - V_{tn})^2

High \(I_D =\) fast digital circuits

Low \(I_D =\) slow digital circuits

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What is fast? High temperature or low temperature?

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It depends on \(V_{DD}\)

Fast corner - Mff (high mobility, low threshold voltage) - High \(V_{DD}\) - High or low temperature

Slow corner - Mss (low mobility, high threshold voltage) - Low \(V_{DD}\) - High or low temperature

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How do we fix temperature variation?

Accept it, or don't use this circuit.

If you need stability over temperature, use 7.3.2 and 7.3.4 in CJM (SUN_BIAS_GF130N)

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Random Variation

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\ell = \mu_p C_{ox} \frac{W}{L}

I_D = \frac{1}{2} \ell (V_{GS} - V_{tp})^2

Due to doping , length, width, \(C_{ox}\), \(V_{tp}\), ... random variation

\ell_1 \ne \ell_2

V_{tp1} \ne V_{tp2}

As a result \(I_1 \ne I_2\), but we can make them close.

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Pelgrom's law [@pelgrom89]

Given a random gaussian process parameter \(\Delta P\) with zero mean, the variance is given by

\sigma^2 (\Delta P) = \frac{A^2_P}{WL} + S_{P}^2 D^2

where \(A_P\) and \(S_P\) are measured, and \(D\) is the distance between devices

Assume closely spaced devices (\(D \approx 0\)) \(\Rightarrow \sigma^2 (\Delta P) = \frac{A^2_P}{WL}\)

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Transistors with same \(V_{GS}\) [@kinget05]

\frac{\sigma_{I_D}^2}{I_D^2} = \frac{1}{WL}\left[\left(\frac{gm}{I_D}\right)^2 \sigma_{vt}^2 + \frac{\sigma_{\ell}^2}{\ell^2}\right]

Valid in weak, moderate and strong inversion

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\(\frac{\sigma_{I_D}^2}{I_D^2} = \frac{1}{WL}\left[\left(\frac{gm}{I_D}\right)^2 \sigma_{vt}^2 + \frac{\sigma_{\ell}^2}{\ell^2}\right]\) \(\frac{\sigma_{I_D}}{I_D} \propto \frac{1}{\sqrt{WL}}\)

Assume \(\frac{\sigma_{I_D}}{I_D} = 10\%\), We want \(5\%\), how much do we need to change WL?

\frac{\frac{\sigma_{I_D}}{I_D}}{2} \propto \frac{1}{2\sqrt{WL}} = \frac{1}{\sqrt{4WL}}

We must quadruple the area to half the standard deviation

\(1 \%\) would require 100 times the area

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What else can we do?

\frac{\sigma_{I_D}^2}{I_D^2} = \frac{1}{WL}\left[\left(\frac{gm}{I_D}\right)^2 \sigma_{vt}^2 + \frac{\sigma_{\ell}^2}{\ell^2}\right]

Strong inversion \(\Rightarrow \frac{gm}{I_D} = \frac{2}{V_{eff}} = low\)

Weak inversion \(\Rightarrow \frac{gm}{I_D} = \frac{q}{n k T} \approx 25\)

Current mirrors achieve best matching in strong inversion

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\frac{\sigma_{I_D}^2}{I_D^2} = \frac{1}{WL}\left[\left(\frac{gm}{I_D}\right)^2 \sigma_{vt}^2 + \frac{\sigma_{\ell}^2}{\ell^2}\right]

\sigma_{I_D}^2 = \frac{1}{WL}\left[gm^2 \sigma_{vt}^2 + I_D^2\frac{\sigma_{\ell}^2}{\ell^2}\right]

Offset voltage for a differential pair

i_o = i_{o+} - i_{o-} = g_m v_i = g_m (v_{i+} - v_{i-})

\sigma_{v_i}^2 = \frac{\sigma_{I_D}^2}{gm^2} = \frac{1}{WL}\left[\sigma_{vt}^2 + \frac{I_D^2}{gm^2}\frac{\sigma_{\ell}^2}{\ell^2}\right]

High \(\frac{gm}{I_D}\) is better (best in weak inversion)

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Transistor Noise

Thermal noise Random scattering of carriers in the channel \(PSD_{TH}(f) = \text{Constant}\)

Popcorn noise Carriers get "stuck" in oxide traps (dangling bonds) for a while. Can cause a short-lived (seconds to minutes) shift in threshold voltage \(PSD_{GR}(f) \propto \text{Lorentzian shape} \approx \frac{A}{1 + \left(\frac{f}{f_0}\right)^2}\)

Flicker noise Assume there are many sources of popcorn noise at different energy levels and time constants, then the sum of the spectral densities approaches flicker noise. \(PSD_{flicker}(f) \propto \frac{1}{f}\)

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Noise equations

Thermal noise current at the drain

\overline{i_{nd}^2} = 4 k T \gamma g_m \Delta f

\gamma \approx 2/3 \text{ (long channel), } 1 \text{ to } 2 \text{ (short channel)}

Flicker noise voltage at the gate

\overline{v_{ng}^2} = \frac{K_f}{W L C_{ox} f} \Delta f

Noise corner, where the two are equal

f_c = \frac{K_f}{W L C_{ox}} \frac{g_m}{4 k T \gamma}

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Summary

The gate controls a barrier: weak inversion is exponential, strong inversion is quadratic
Transconductance is two times current over overdrive, or current over nVT - whichever is smaller
Intrinsic gain falls with overdrive and with shorter length
Four capacitances set the speed: Cgs usually dominates the poles (it is the largest, think current mirrors), and Cgd gets multiplied by Miller
Match with area (Pelgrom), buy speed with overdrive and short length, buy gain with long length
Nothing is constant: supply, process, temperature, mismatch and noise all move - design for the box, not the point

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Would you like to know more?

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