CMOS Logic

Analog transistor to digital transistor

1

NMOS current (W = 0.4u L=0.15u) as a function of \(V_{GS}\) and \(V_{DS}\)

_{_{dicex/lectures/l13/mos.py}}

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Gate	NMOS	PMOS
VDD	ON	OFF
VDD -> VSS	X	X
VSS -> VDD	X	X
VSS	OFF	ON

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Gate	NMOS	PMOS
1	ON	OFF
1 -> 0	X	X
0 -> 1	X	X
0	OFF	ON

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CMOS static logic assumptions

NMOS source is connected to low potential

\(V_{GS} > V_{TH}\) when \(V_G = V_{DD}\)

PMOS source is connected to high potential

\(V_{GS} < V_{TH}\) when \(V_G = 0\)

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8

Don't break rules unless you know exactly why it will be OK

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Logic cells

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CMOS static logic is inverting

A	Y
1	0
0	1

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_{PD = Pull-down PU = Pull-up}

logic => [0,1,Z,X];

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Pull-up series

A	B	Y
0	0	1
0	1	Z
1	0	Z
1	1	Z

Pull-up parallel

A	B	Y
0	0	1
0	1	1
1	0	1
1	1	Z

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Pull-down series

A	B	Y
0	0	Z
0	1	Z
1	0	Z
1	1	0

Pull-down parallel

A	B	Y
0	0	Z
0	1	0
1	0	0
1	1	0

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Rules for inverting logic

Pull-up OR => PMOS in series => POS AND => PMOS in parallel => PAP

Pull-down OR => NMOS in parallel => NOP AND => NMOS in series => NAS

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\text{Y} = \overline{\text{AB}} = \text{NOT ( A AND B)}

AND PU => PMOS in parallel PD => NMOS in series

A	B	_{NOT(A AND B)}
0	0	1
0	1	1
1	0	1
1	1	0

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\(\text{Y} = \overline{\text{A + B}} = \text{NOT ( A OR B)}\)

OR PU => PMOS in series PD => NMOS in parallel

A	B	_{NOT(A OR B)}
0	0	1
0	1	0
1	0	0
1	1	0

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SR-Latch

Use boolean expressions to figure out how gates work.

Remember De-Morgan

\(\overline{AB} = \overline{A}+ \overline{B}\) \(\overline{A+B} = \overline{A} \cdot \overline{B}\)

Q = \overline{R \overline{Q}} = \overline{R} + \overline{\overline{Q}} = \overline{R} + Q

\overline{Q} = \overline{S Q} = \overline{S} + \overline{Q} = \overline{S} + \overline{Q}

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\(Q = \overline{R} + Q\) ,

\overline{Q} =\overline{S} + \overline{Q}

S	R	Q	~Q
0	0	X	X
0	1	0	1
1	0	1	0
1	1	Q	~Q

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D-Latch (16 transistors)

C	D	Q	~Q
0	X	Q	~Q
1	0	0	1
1	1	1	0

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Other logic cells

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What about \(\text{Y} = \text{AB}\) and \(\text{Y} = \text{A} + \text{B}\)?

\text{Y} = \text{AB} = \overline{\overline{\text{AB}}}

Y = A AND B = NOT( NOT( A AND B ) )

\text{Y} = \text{A+B} = \overline{\overline{\text{A+B}}}

Y = A OR B = NOT( NOT( A OR B ) )

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AOI22: and or invert

Y = NOT( A AND B OR C AND D)

\text{Y} = \overline{\text{AB} + \text{CD}}

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Tristate inverter

E	A	Y
0	0	Z
0	1	Z
1	0	1
1	1	0

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Mux

S	Y
0	NOT(P1)
1	NOT(P0)

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D-Latch (12 transistors)

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D-Flip Flop (< 26 transistors)

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There are other types of logic

True single phase clock (TSPC) logic
Pass transistor logic
Transmission gate logic
Differential logic
Dynamic logic

Consider other types of logic "rule breaking", so you should know why you need it.

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_{_{Dynamic logic => A Compiled 9-bit 20-MS/s 3.5-fJ/conv.step SAR ADC in 28-nm FDSOI for Bluetooth Low Energy Receivers [@wulff17]}}

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Speed

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Flip-flops and speed

dicex/lib/SUN_TR_GF130N.spi:

.SUBCKT DFRNQNX1_CV D CK RN Q QN AVDD AVSS
XA0 AVDD AVSS TAPCELLB_CV
XA1 CK RN CKN AVDD AVSS NDX1_CV
XA2 CKN CKB AVDD AVSS IVX1_CV
XA3 D CKN CKB A0 AVDD AVSS IVTRIX1_CV
XA4 A1 CKB CKN A0 AVDD AVSS IVTRIX1_CV
XA5 A0 A1 AVDD AVSS IVX1_CV
XA6 A1 CKB CKN QN AVDD AVSS IVTRIX1_CV
XA7 Q CKN CKB RN QN AVDD AVSS NDTRIX1_CV
XA8 QN Q AVDD AVSS IVX1_CV
.ENDS

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Setup time: How long before clk does the data need to change

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Hold time: How long after clk can the data change

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Digital timing challenge: Estimate and analyze all delays over PVT

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Timing analysis

43

Analyze arrival times of all nodes in a combinatorial circuit

arrival_i = max_{j \in fanin(i)}{arrival_j} + t_{pd_i} \Rightarrow a_i = max_{j \in fanin(i)}{a_j} + t_{pd_i}

\[slack_i = required_i - arrival_i\]

Positive slack (over PVT[^1]) => Timing is OK Negative slack (over PVT[^1]) => Timing is not OK

[^1]: PVT => Process, Voltage, Temperature

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Timing analysis tools

Commercial Cadence Tempus

Synopsys PrimeTime

Free OpenTimer

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Every gate must be simulated to provide behavior over input transition and load capacitance

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All analog blocks must have associated liberty file to describe behavior and timing paths _{If you integrate analog into digital top flow}

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Gate Delay

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Delay definitions

Parameter	Name	Description
t_pdr	max rising propagation delay	input to rising output cross 50 %
t_pdf	max falling propagation delay	input to falling output cross 50 %
t_pd	propagation delay	t_pd = (t_pdr + t_pdf)/2
t_r	rise time	20 % to 80 %

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Parameter	Name	Description
t_f	fall time	80 % to 20 %
t_cdr	min rising contamination delay	input to rising output cross 50 %
t_cdf	min falling contamination delay	input to falling output cross 50 %
t_cd	contamination delay	t_cd = (t_cdr + t_cdf)/2

54

Delay estimation

How can we get a reasonably accurate hand calculation model of delay?

C \approx 1 \text{ fF}/\mu\text{m}

R \approx 1 \text{ k}\Omega\mu\text{m}

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Inverter with inverter load

\(C \approx 1 \text{ fF}/\mu\text{m}\), \(R \approx 1 \text{ k}\Omega\mu\text{m}\)

t_{pd} = R \times 6C = 6RC

\(t_{pd} = 6 \times 1 \times 10^{3} \times 1 \times 10^{-15} \text{ s}\)

t_{pd} = 6 \times 10^{-12} = 6 \text{ ps}

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Elmore Delay

t_{pd} \approx \sum_{\text{nodes}}{R_{\text{nodes}-to-source} C_i}

\[= R_1C_1 + (R_1 + R_2)C_2 + ... + (R_1 + R_2 + ... + R_N) C_N\]

Good enough for hand calculation

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Delay components

Parasitic delay (p)

p = 9 or 12 RC

Independent of load capacitance

Effort delay (f)

f = 5h RC

Proportional to load capacitance

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Let's use process independent unit \(d = \frac{d_{real}}{\tau}\), \(\tau = 3 RC\)

Parasitic delay \(\Rightarrow p = 12 RC / 3 RC = 4\)

Effort delay \(\Rightarrow f = 5h RC / 3RC = \frac{5}{3} h\)

Delay \(\Rightarrow d = f + p = \frac{5}{3}h + 4\)

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Logical effort (g) is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current

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Parasitic delay \(\Rightarrow p = 4\)

Logic effort \(\Rightarrow g = \frac{5}{3}\)

Electrical effort \(\Rightarrow h = 1\)

Effort \(\Rightarrow f = gh\)

Delay \(\Rightarrow d = f + p = gh + p = 5\frac{2}{3}\)

Real delay \(\Rightarrow d = 5\frac{2}{3} \times 3 \text{ ps} = 17 \text{ ps}\)

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Modern IC timing analysis requires computers with advanced programs[^2]

[^2]: Opportunity for good programmers

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Best number of stages

64

Which has shortest delay?

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H = C_{cout}/C_{in} = 64

G = \prod{g_i} = \prod{1} = 1

\[B = 1\]

\[F = GBH = 64\]

One stage, with Sutherland's classic \(p \approx 1\) per inverter \(f = 64 \Rightarrow D = 64 + 1 = 65\)

Three stage with \(f=4\) \(D_F = 12, p = 3 \Rightarrow D = 12 + 3 = 15\)

For close to optimal delay, use \(f = 4\) _{_{(Used to be \(f=e\))}}

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Trends

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Attack vector

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module counter(
               output logic [WIDTH-1:0] out,
               input logic              clk,
               input logic              reset
               );

   parameter WIDTH = 8;

   logic [WIDTH-1:0]                    count;
   always_comb begin
      count = out + 1;
   end

   always_ff @(posedge clk or posedge reset) begin
      if (reset)
        out <= 0;
      else
        out <= count;
   end

endmodule // counter

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.SUBCKT counter out_7 out_6 out_5 out_4 out_3 out_2 out_1 out_0 clk reset AVDD AVSS
* SPICE netlist generated by Yosys 0_9 (git sha1 1979e0b1, gcc 10_3_0-1ubuntu1~20_10 -fPIC -Os)
X0 out_2 1 AVDD AVSS IVX1_CV
X1 out_3 2 AVDD AVSS IVX1_CV
X2 out_4 3 AVDD AVSS IVX1_CV
X3 out_5 4 AVDD AVSS IVX1_CV
X4 out_6 5 AVDD AVSS IVX1_CV
X5 out_0 6 AVDD AVSS IVX1_CV
X6 out_1 7 AVDD AVSS IVX1_CV
X7 6 7 8 AVDD AVSS NRX1_CV
X8 out_0 out_1 9 AVDD AVSS NDX1_CV
X9 1 9 10 AVDD AVSS NRX1_CV
X10 10 11 AVDD AVSS IVX1_CV
X11 2 11 12 AVDD AVSS NRX1_CV
X12 out_3 10 13 AVDD AVSS NDX1_CV
X13 out_3 10 14 AVDD AVSS NRX1_CV
X14 12 14 15 AVDD AVSS NRX1_CV
X15 3 13 16 AVDD AVSS NRX1_CV
X16 16 17 AVDD AVSS IVX1_CV
X17 out_4 12 18 AVDD AVSS NRX1_CV
X18 16 18 19 AVDD AVSS NRX1_CV
X19 4 17 20 AVDD AVSS NRX1_CV
X20 out_5 16 21 AVDD AVSS NDX1_CV
X21 out_5 16 22 AVDD AVSS NRX1_CV
X22 20 22 23 AVDD AVSS NRX1_CV
X23 5 21 24 AVDD AVSS NRX1_CV
X24 out_6 20 25 AVDD AVSS NRX1_CV
X25 24 25 26 AVDD AVSS NRX1_CV
X26 out_7 24 27 AVDD AVSS NRX1_CV
X27 out_7 24 28 AVDD AVSS NDX1_CV
X28 28 29 AVDD AVSS IVX1_CV
X29 27 29 30 AVDD AVSS NRX1_CV
X30 out_0 out_1 31 AVDD AVSS NRX1_CV
X31 8 31 32 AVDD AVSS NRX1_CV
X32 out_2 8 33 AVDD AVSS NRX1_CV
X33 10 33 34 AVDD AVSS NRX1_CV
X34 35 clk AVSS reset out_0 35 AVDD AVSS DFSRQNX1_CV
X35 32 clk AVSS reset out_1 36 AVDD AVSS DFSRQNX1_CV
X36 34 clk AVSS reset out_2 37 AVDD AVSS DFSRQNX1_CV
X37 15 clk AVSS reset out_3 38 AVDD AVSS DFSRQNX1_CV
X38 19 clk AVSS reset out_4 39 AVDD AVSS DFSRQNX1_CV
X39 23 clk AVSS reset out_5 40 AVDD AVSS DFSRQNX1_CV
X40 26 clk AVSS reset out_6 41 AVDD AVSS DFSRQNX1_CV
X41 30 clk AVSS reset out_7 42 AVDD AVSS DFSRQNX1_CV
V0 count_0 35 DC 0
V1 43 out_2 DC 0
V2 44 out_3 DC 0
V3 count_3 15 DC 0
V4 45 out_4 DC 0
V5 count_4 19 DC 0
V6 46 out_5 DC 0
V7 count_5 23 DC 0
V8 47 out_6 DC 0
V9 count_6 26 DC 0
V10 48 out_7 DC 0
V11 count_7 30 DC 0
V12 49 out_0 DC 0
V13 50 out_1 DC 0
V14 count_1 32 DC 0
V15 count_2 34 DC 0
.ENDS

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dicex/sim/verilog/counter_sv/counter_attack_tb.cir

VDDA AVDD_ATTACK 0 dc 0.5 pulse(1.5 0.6 tcd trf trf tapw taper)

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Pick two

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Power

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What is power?

Instantanious power: \(P(t) = I(t)V(t)\)

Energy : \(\int_0^T{P(t)dt}\) [J]

Average power: \(\frac{1}{T} \int_0^T{P(t)dt}\) [W or J/s]

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Power dissipated in a resistor

Ohm's Law \(V_R = I_R R\)

P_R = V_R I_R = I_R^2 R = \frac{V_R^2}{R}

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Charging a capacitor to VDD

Capacitor differential equation \(I_C = C\frac{dV}{dt}\)

E_{C} = \int_0^\infty{I_C V_C dt} = \int_0^\infty{ C \frac{dV}{dt} V_C dt} = \int_0^{V_C}{C V dV} = C\left[\frac{V^2}{2}\right]_0^{V_{DD}}

E_{C} = \frac{1}{2} C V_{DD}^2

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Energy to charge a capacitor to a voltage VDD

E_{C} = \frac{1}{2} C V_{DD}^2

I_{VDD} = I_C = C \frac{dV}{dt}

E_{VDD} = \int_0^\infty{I_{VDD} V_{DD} dt} = \int_0^\infty{C \frac{dV}{dt} V_{DD} dt} = C V_{DD}\int_0^{V_{DD}}{dV} = C V_{DD}^2

Only half the energy is stored on the capacitor, the rest is dissipated in the PMOS

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Discharging a capacitor to 0

E_{C} = \frac{1}{2} C V_{DD}^2

Voltage is pulled to ground, and the power is dissipated in the NMOS

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Power consumption of digital circuits

E_{VDD} = C V_{DD}^2

In a clock distribution network (chain of inverters), every output is charged once per clock cycle

P_{VDD} = C V_{DD}^2 f

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Sources of power dissipation in CMOS logic

\(P_{total} = P_{dynamic} + P_{static}\)

Dynamic power dissipation

Charging and discharging load capacitances

short-circut current, when PMOS and NMOS conduct at the same time

P_{dynamic} = P_{switching} + P_{short circuit}

Static power dissipation

Subthreshold leakage in OFF transistors

Gate leakage (tunneling current) through gate dielectric

Source/drain reverse bias PN junction leakage

P_{static} = \left( I_{sub} + I_{gate} + I_{pn} \right) V_{DD}

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Switching Power in logic gates

Only output node transitions from low to high consume power from \(V_{DD}\)

Define \(P_i\) to be the probability that a node is 1

Define \(\overline{P_i} = 1 - P_i\) to be the probability that a node is 0

Define activity factor (\(\alpha_i\)) as the probability of switching a node from 0 to 1

If the probabilty is uncorrelated from cycle to cycle

\alpha_i = \overline{P_i}P_i

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Switching probability

Random data \(P = 0.5\), \(\alpha = 0.25\)

Clocks \(\alpha = 1\)

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Assume \(P = P_A = P_B = P_C = P_D = \frac{1}{2}\)

P_X = P_Z = 1 - P P = 1 - \frac{1}{4} = \frac{3}{4}

\(\overline{P_X} = \overline{P_Y} = \frac{1}{4}\)

P_Y = \frac{1}{4} \times \frac{1}{4} = \frac{1}{16}

\alpha = \frac{1}{16}\left(1 - \frac{1}{16}\right) = \frac{15}{16}\frac{1}{16} = \frac{15}{256}

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\(\overline{\overline{\text{AB}} + \overline{\text{CD}}}\)

Use De Morgan first \(\overline{A+B} = \overline{A} \cdot \overline{B}\)

\overline{\overline{\text{AB}} + \overline{\text{CD}}} = \overline{\overline{\text{AB}}} \overline{\overline{\text{CD}}} = ABCD

\Rightarrow P_Y = P_A P_B P_C P_D = \left(\frac{1}{2}\right)^4 = \frac{1}{16}

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\(P_{tot} = \alpha C V_{DD}^2 f\)

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Strategies to reduce dynamic power

Stop clock
Stop activity
Reduce clock frequency
Turn off VDD
Reduce VDD

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Stop clock [^3]

[^3]: Often called clock gating

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Stop activity

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Reduce frequency

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Turn off power supply [^4]

[^4]: Often called power gating

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Reduce power supply

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Energy-Delay Product

EDP = k\frac{C^2 V_{DD}^3}{(V_{DD}- V_t)^{\text{1 to 2}}}

Differentiating with respect to \(V_{DD}\) and setting the result to \(0\) it's possible to work out that

V_{DD-opt} = \frac{3}{3-\text{1 to 2}}V_t \in[1.5,3]V_{t}

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Wires

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Wire geometry

Pitch = w + s

Aspect ratio (AR) = t/w

These days \(AR \approx 2\)

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Metal stack

Often 5 - 10 layers of metal

Metal	Material	Thickness	Purpose
Metal 1	Copper	Thin	in gate routing
Metal 3 - 5	Copper	Thicker	Between gates routing
RDL	Aluminium	Ultra thick	Can tolerate high forces during wire bonding.

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Metal routing rules on IC

Odd numbers metals => Horizontal routing (as far as possible)

Even numbers metals => Vertical routing (as far as possible)

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Modeling Interconnect

Resistance narrow size impedes flow

Capacitance through under the leaky pipes

Inductance paddle wheel intertia opposes changes in flow rate

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Lumped model

Use 1-segment \(\pi\)-model for Elmore delay

C/2   R   C/2
---/\/\/\---
 |        |
---      ---
---      --- 
 |        |
---      --- 
 -        -

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Wire resistance

\text{resistivity} \Rightarrow \rho \text{ [} \Omega\text{m]}

R = \frac{\rho}{t}\frac{l}{w} = R_\square \frac{l}{w}

R_\square = \text{sheet resistance [} \Omega/\square \text{]}

To find resistance, count the number of squares

R = R_\square \times \text{\# of squares}

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Most wires: Copper

\(R_{sheet-m1} \approx \frac{1.7 \mu\Omega cm}{200 nm} \approx 0.1 \Omega/\square\)
\(R_{sheet-m9} \approx \frac{1.7 \mu\Omega cm}{3 \mu m} \approx 0.006 \Omega/\square\)

Pitfalls

Cu atoms diffuse into silicon and can cause damage

Must be surrounded by a diffusion barrier

Difficult high current densities (mA/\(\mu\)m) and high temperature (125 C)

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Contacts

Contacts and vias can have 2-20 \(\Omega\)

Must use many contacts/vias for high current wires

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Wire Capacitance

Dense wires has about \(0.2 \text{ fF/}\mu\text{m}\)

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FSM

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Mealy machine

An FSM where outputs depend on current state and inputs

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Moore machine

An FSM where outputs depend on current state

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Mealy versus Moore

Parameter	Mealy	Moore
Outputs	depend on input and current state	output depend on current state
States	Same, or fewer states than Moore
Inputs	React faster to inputs	Next clock cycle
Outputs	Can be asynchronous	Synchronous
States	Generally requires fewer states for synthesis	More states than Mealy
Counter	A counter is not a mealy machine	A counter is a Moore machine
Design	Can be tricky to design	Easy

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dicex/sim/counter_sv/counter.v

module counter(
               output logic [WIDTH-1:0] out,
               input logic              clk,
               input logic              reset
               );
   parameter WIDTH                      = 8;
   logic [WIDTH-1:0]                    count;

   always_comb begin
      count = out + 1;
   end

   always_ff @(posedge clk or posedge reset) begin
      if (reset)
        out <= 0;
      else
        out <= count;
   end

endmodule // counter

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Battery charger FSM

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Li-Ion batteries

Most Li-Ion batteries can tolerate 1 C during fast charge

For Biltema 18650 cells: \(1\text{ C} = 2950\text{ mA}\) \(0.1\text{ C} = 295\text{ mA}\)

Most Li-Ion need to be charged to a termination voltage of 4.2 V

Too high termination voltage, or too high charging current can cause growth of lithium dendrites, that short + and -. Will end in flames. Always check manufacturer datasheet for charging curves and voltages

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Battery charger - Inputs

Voltage above \(V_{TRICKLE}\)

Voltage close to \(V_{TERM}\)

If voltage close to \(V_{TERM}\) and current is close to \(I_{TERM}\), then charging complete

If charging complete, and voltage has dropped (\(V_{RECHARGE}\)), then start again

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Battery charger - States

Trickle charge (0.1 C)

Fast charge (1 C)

Constant voltage

Charging complete

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One way to draw FSMs - Graphviz

digraph finite_state_machine {
    rankdir=LR;
    size="8,5"

    node [shape = doublecircle, label="Trickle charger", fontsize=12] trkl;
    node [shape = circle, label="Fast charge", fontsize=12] fast;
    node [shape = circle, label="Const. Voltage", fontsize=12] vconst;
    node [shape = circle, label="Done", fontsize=12] done;

    trkl -> trkl [label="vtrkl = 0"];
    trkl -> fast [label="vtrkl = 1"];
    fast -> fast [label="vterm = 0"];
    fast -> vconst [label="vterm = 1"];
    vconst-> vconst [label="iterm = 0"];
    vconst-> done [label="iterm = 1"];
    done-> done [label="vrchrg = 0"];
    done-> trkl [label="vrchrg = 1"];

}

dot -Tpdf bcharger.dot -o bcharger.pdf

117

module bcharger( output logic trkl,
        output logic fast, 
        output logic vconst,
        output logic done,
        input logic  vtrkl, 
        input logic  vterm, 
        input logic  iterm, 
        input logic  vrchrg,
        input logic  clk, 
        input logic  reset
                    );

   parameter TRLK = 0, FAST = 1, VCONST = 2, DONE=3;
   logic [1:0]                   state;
   logic [1:0]                   next_state;

   //- Figure out the next state
   always_comb begin
      case (state)
        TRLK: next_state = vtrkl ? FAST : TRLK;
        FAST: next_state = vterm ? VCONST : FAST;
        VCONST: next_state = iterm ? DONE : VCONST;
        DONE: next_state = vrchrg ? TRLK :DONE;
        default: next_state = TRLK;
      endcase // case (state)
    end

   //- Control output signals
   always_ff @(posedge clk or posedge reset) begin
      if(reset) begin
         state <= TRLK;
         trkl <= 1;
         fast <= 0;
         vconst <= 0;
         done <= 0;
      end
      else begin
         state <= next_state;
         case (state)
           TRLK: begin
              trkl <= 1;
              fast <= 0;
              vconst <= 0;
              done <= 0;
           end
           FAST: begin
              trkl <= 0;
              fast <= 1;
              vconst <= 0;
              done <= 0;

           end
           VCONST: begin
              trkl <= 0;
              fast <= 0;
              vconst <= 1;
              done <= 0;

           end
           DONE: begin
              trkl <= 0;
              fast <= 0;
              vconst <= 0;
              done <= 1;
           end
         endcase // case (state)
      end // else: !if(reset)
   end
endmodule

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Synthesize FSM with yosys

_{dicex/sim/verilog/bcharger_sv/bcharger.ys}


# read design
read_verilog -sv bcharger.sv;
hierarchy -top bcharger;

# the high-level stuff
fsm; opt; memory; opt;

# mapping to internal cell library
techmap; opt;
synth;
opt_clean;

# mapping flip-flops 
dfflibmap  -liberty ../../../lib/SUN_TR_GF130N.lib

# mapping logic 
abc -liberty ../../../lib/SUN_TR_GF130N.lib

# write synth netlist
write_verilog bcharger_netlist.v
read_verilog  ../../../lib/SUN_TR_GF130N_empty.v
write_spice -big_endian -neg AVSS -pos AVDD -top bcharger bcharger_netlist.sp

# write dot so we can make image
show -format dot -prefix bcharger_synth -colors 1 -width -stretch
clean

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Thanks!

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Summary

CMOS logic is a PMOS pull-up network against an NMOS pull-down: the inverter is the atom
Delay is RC: Elmore for a hand estimate, logical effort for sizing - stage long paths at an effort around four
Registers, combinational clouds and a clock make synchronous design; setup and hold are checked at every capture
Static timing analysis walks every path over PVT: positive slack, or it does not ship
Dynamic power is CV^2 f; leakage is what you pay even when nothing switches

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Would you like to know more?

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