Carsten Wulff 2026
4
Explain why we need Analog SystemVerilog models
Introduction to Analog SystemVerilog
The order of execution of events at the same time-step does not matter
The system is causal. Changes in the future do not affect signals in the past or the now
module counter(
output logic [WIDTH-1:0] out,
input logic clk,
input logic reset
);
parameter WIDTH = 8;
logic [WIDTH-1:0] count;
always_comb begin
count = out + 1;
end
always_ff @(posedge clk or posedge reset) begin
if (reset)
out <= 0;
else
out <= count;
end
endmodule // counter
Assume `clk, reset, out = 0`
Assume event with `clk = 1`
0: Set `out = count` in next event (1)
1: Set `count = out + 1` using
logic (may consume multiple events)
X: no further events
parse spice netlist, and setup partial/ordinary differential equations for node matrix
\[\begin{pmatrix} G_{11} &G_{12} &\cdots &G_{1N} \\ G_{21} &G_{22} &\cdots &G_{2N} \\ \vdots &\vdots &\ddots & \vdots\\ G_{N1} &G_{N2} &\cdots &G_{NN} \end{pmatrix} \begin{pmatrix} v_1\\ v_2\\ \vdots\\ v_N \end{pmatrix}= \begin{pmatrix} i_1\\ i_2\\ \vdots\\ i_N \end{pmatrix}\]
model the non-linear current/voltage behavior between all nodes
numerical methods to compute time evolution
SPICE (Simulation Program with Integrated Circuit Emphasis) published in 1973 by Nagel and Pederson
Commercial - Cadence Spectre - Siemens Eldo - Synopsys HSPICE
Free - Aimspice - Analog Devices LTspice - xyce
Open Source - ngspice
//tt06-sar/src/project.v
module tt_um_TT06_SAR_wulffern (
input wire VGND,
input wire VPWR,
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
`ifdef ANA_TYPE_REAL
input real ua_0,
input real ua_1,
`else
// analog pins
inout wire [7:0] ua,
`endif
input wire ena,
input wire clk,
input wire rst_n
);
//tt06-sar/src/tb_ana.v
`ifdef ANA_TYPE_REAL
real ua_0 = 0;
real ua_1 = 0;
`else
tri [7:0] ua;
logic uain = 0;
assign ua = uain;
`endif
`ifdef ANA_TYPE_REAL
always #100 begin
ua_0 = \(sin(2*3.14*1/7750*\)time);
ua_1 = -\(sin(2*3.14*1/7750*\)time);
end
`endif
//tt06-sar/src/tb_ana.v
tt_um_TT06_SAR_wulffern dut (
.VGND(VGND),
.VPWR(VPWR),
.ui_in(ui_in),
.uo_out(uo_out),
.uio_in(uio_in),
.uio_out(uio_out),
.uio_oe(uio_oe),
`ifdef ANA_TYPE_REAL
.ua_0(ua_0),
.ua_1(ua_1),
`else
.ua(ua),
`endif
.ena(ena),
.clk(clk),
.rst_n(rst_n)
);
#tt06-sar/src/Makefile
runa:
iverilog -g2012 -o my_design -c tb_ana.fl -DANA_TYPE_REAL
vvp -n my_design
rund:
iverilog -g2012 -o my_design -c tb_ana.fl
vvp -n my_design
//tt06-sar/src/project.v
//Main SAR loop
always_ff @(posedge clk or negedge clk) begin
if(~ui_in[0]) begin
state <= OFF;
tmp = 0;
dout = 0;
end
else begin
if(OFF) begin
end
else if(clk == 1) begin
state = SAMPLE;
end
else if(clk == 0) begin
state = CONVERT;
`ifdef ANA_TYPE_REAL
smpl = ua_0 - ua_1;
tmp = smpl;
for(int i=7;i>=0;i--) begin
if(tmp >= 0) begin
tmp = tmp - lsb*2**(i-1);
if(i==7)
dout[i] <= 0;
else
dout[i] <= 1;
end
else begin
tmp = tmp + lsb*2**(i-1);
if(i==7)
dout[i] = 1;
else
dout[i] = 0;
end
end
`else
if(tmp == 0) begin
dout[7] <= 1;
tmp <= 1;
end
else begin
dout[7] <= 0;
tmp = 0;
end
`endif
end
state = next_state;
end // else: !if(~ui_in[0])
end // always_ff @ (posedge clk)
//tt06-sar/src/project.v
always @(posedge done) begin
state = DONE;
sampled_dout = dout;
end
always @(state) begin
if(state == OFF)
#2 done = 0;
else if(state == SAMPLE)
#1.6 done = 0;
else if(state == CONVERT)
#115 done = 1;
end
