TFE4188 - Lecture 7

Voltage regulation

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Goal

Why do we need voltage regulation

Introduction to linear regulators

Introduction to switched regulators

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Why

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Voltage source

	Chemistry	Voltage [V]
Primary Cell	LiFeS2 , Zn/Alk/MnO2 , LiMnO2	0.8 - 3.6
Secondary Cell	Li-Ion	2.5 - 4.3
USB	-	4.0 - 6.5 (20)

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Core voltage

Node [nm]	Voltage [V]
180	1.8
130	1.5
55	1.2
22	0.8

IO voltage

Voltage [V]
5.0
3.0
1.8
1.2

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Name	Voltage	Min [nA]	Max [mA]	PWR DR [dB]
VDD_VBUS	5	10	500	77
VDD_VBAT	4	10	400	76
VDD_IO	1.8	10	50	67
VDD_CORE	0.8	10	350	75

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Linear Regulators

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PMOS pass-fet

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Parameter	Description	Unit
Load regulation	How much does the output voltage change with load current	V/A
Line regulation	How much does the output voltage change with input voltage	V/V
Power supply rejection ratio	What is the transfer function from input voltage to output voltage? The PSRR at DC is the line regulation	dB
Max current	How much current can be delivered through the pass-fet?	A
Quiescent current	What is the current used by the regulator	A
Settling time	How fast does the output voltage settle at a current step	s

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NMOS pass-fet

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Testbench for LDO pass-fet

* Pass-fet
XM1 OUT G VDD VDD sky130_fd_pr__pfet_01v8 
+ L=0.252 W=11.52 nf=2 ...  m=1000

* Reference
VREF VREF 0 dc 0.8

* OTA
BOTA G 0 V=(1 + tanh(-1000*(v(vref) -v(out) )))/2*{AVDD}

* Load cap
CL OUT 0 1u

* Current load
ILOAD OUT 0 pwl 0 0 1u 0 50u 0.5

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Switched Regulators

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Principles of switched regulators

There is a big difference between the idea for a circuit, and the actual implementation. A real DC/DC implementation may seem overwhelming.

Just look at figure 7 in A 10-MHz 2–800-mA 0.5–1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes [@kim18]

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Inductive BUCK DC/DC

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Capacitive BUCK DC/DC

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Inductive BOOST DC/DC

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Capacitive BOOST DC/DC

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Inductive DC/DC converter details

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I_x(t) = \frac{1}{L} \int{V_x(t) dt}

V_o(t) = \frac{1}{C} \int{(I_x(t) - I_o(t))}dt

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Pulse width modulation (PWM)

Jupyter PWM BUCK model - interactive - closed loop with type 3

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Pulsed Frequency Mode (PFM)

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Jupyter PFM BUCK model - interactive

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Summary

Supply planning comes first: which blocks share a regulator, what noise they inject, what sequence they wake in
A PMOS pass linear regulator gives the lowest dropout but a hard loop (output pole moves with load); the NMOS follower is easy to stabilize but costs a V_GS of headroom
Linear regulators burn (V_in - V_out)/V_in of the power - fine for quiet rails, ruinous for big steps
Inductive DC/DC converters move charge through an inductor at ~90% efficiency: PWM at heavy load, PFM pulses at light load
Line/load regulation and PSRR are the datasheet numbers; the transient response to a load step is what the digital core actually feels

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Would you like to know more?

Thanks!

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