TFE4188 - Advanced Integrated Circuits

Lecture 1 - Introduction

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Who

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Carsten Wulff carstenw@ntnu.no

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How I see our roles

Professors: Guide students on what is impossible, possible, and hints on what might be possible

Ph.D students: Venture into the unknown and make something (more) possible

Master students: Learn all that is currently possible

Bachelor students: Learn how to make complicated into easy

Industry: Take what is possible, and/or complicated, and make it easy

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Why

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I want you to learn the skills necessary to make your own ICs

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There will always be analog circuits, because the real world is analog

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_{https://circuitcellar.com/insights/tech-the-future/kinget-the-world-is-analog/}

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Life of an analog designer: Schematic Design

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Life of an analog designer: Layout Design

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Status	Abstraction	Design	Layout	Why
:construction:	Chip	SystemVerilog	digital	Complex connections, few analog interfaces
:construction:	Module	SystemVerilog	digital	Large amount of digital signals, few analog signals
:warning:	Block	Schematic	programmatic	Large amount of critical analog interfaces, few digital
:white_check_mark:	Cell	Netlist/JSON	compiled	Few analog interfaces, few digital interfaces
:white_check_mark:	Device	JSON	compiled	Polygon pushing
:white_check_mark:	Technology	JSON/Rules	compiled	Custom for each technology

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Will you tape-out an IC?

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https://tinytapeout.com/runs/

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https://analogicus.com/aic2026

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Project flow support: Confluence, JIRA, risk management (DFMEA), failure analysis (8D)
Language: English, Writing English (Latex, Word, Email)
Psychology: Personalities, convincing people, presentations (Powerpoint, Deckset), stress management (what makes your brain turn off?)
DevOps: Linux, build systems (CMake, make, ninja), continuous integration (bamboo, jenkins), version control (git), containers (docker), container orchestration (swarm, kubernetes)
Programming: Python, C, C++, Matlab _{Since 1999 I’ve programmed in Python, Go, Visual BASIC, PHP, Ruby, Perl, C#, SKILL, Ocean, Verilog-A, C++, BASH, AWK, VHDL, SPICE, MATLAB, ASP, Java, C, SystemC, Verilog, Assembler, and probably a few I’ve forgotten.}
Firmware: signal processing, algorithms, software architecture, security
Infrastructure: Power management, reset, bias, clocks
Domains: CPUs, peripherals, memories, bus systems
Sub-systems: Radio’s, analog-to-digital converters, comparators
Blocks: Analog Radio, Digital radio baseband
Modules: Transmitter, receiver, de-modulator, timing recovery, state machines
Designs: Opamps, amplifiers, current-mirrors, adders, random access memory blocks, standard cells
Tools: schematic, layout, parasitic extraction, synthesis, place-and-route, simulation, (System)Verilog, netlist
Physics: transistor, pn junctions, quantum mechanics

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Zen of IC design (stolen from Zen of Python)

Beautiful is better than ugly.
Explicit is better than implicit.
Simple is better than complex.
Complex is better than complicated.
Readability counts (especially schematics).
Special cases aren't special enough to break the rules.
Although practicality beats purity.

In the face of ambiguity, refuse the temptation to guess.
There should be one and preferably only one obvious way to do it.
Now is better than never.
Although never is often better than right now.
If the implementation is hard to explain, it's a bad idea.
If the implementation is easy to explain, it may be a good idea.

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echo "Find a problem that you really want to solve,"\
     "and learn programming to solve it."\
     "There is no point in saying 'I want to learn programming',"\
     "then sit down with a book to read about programming,"\
     "and expect that you will learn programming that way."\
     "It will not happen. The only way to learn programming"\
     "is to do it, a lot." \
     |perl -pe 's/programming/analog design/ig'

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Analog Design Process

Define the problem, what are you trying to solve?
Find a circuit that can solve the problem (papers, books)
Find right transistor sizes. What transistors should be weak inversion, strong inversion, or don't care?
Write a verification plan (ask chat). Plan to simulate everything that could go wrong.
Check operating region of transistors (.op)
Check key parameters (.dc, .ac, .tran)
Check function. Exercise all inputs. Check all control signals

Check key parameters in all corners. Check mismatch (Monte-Carlo simulation)
Do layout, and check it's error free. Run design rule checks (DRC). Check layout versus schematic (LVS)
Extract parasitics from layout. Resistance, capacitance, and inductance if necessary.
On extracted parasitic netlist, check key parameters in all corners and mismatch (if possible).
If everything works, then you're done.

On failure, go back as far as necessary

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My Goal

You are the one that must teach yourself everything.

My guide role:

Enable you to read the books on integrated circuits
Enable you to read papers (latest research)
Correct misunderstandings on the topic
Answer any questions you have on the chapters

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Plan

Lectures: Friday at 08:15 in R90

It helps if you read the notes before the lecture, and have questions. Notes at aic2026

The "lectures" will be Q & A's on the topic. If no questions, then I'll ramble on.

Project Hours: Friday at 10:15 in KJL4

Groups meet, and work on project.

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Exam

May/June?
4 hours
A - F grade (F = Fail)
Counts for 55 % of the grade

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Compulsory exercise (Milestone 0)

Follow: Sky130nm Tutorial

Submit link to your github repository on blackboard

For example, my repository: JNW_EX_SKY130A

The exercise is designed to teach you everything the skills you need to do the project

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Project

Counts for 45 % of the grade

No exam without project.

Strict deadline 1'st of May. If you hand in 2'nd of May at 00:00:01, then you fail the course.

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Software

Open source software (xschem, ngspice, sky130A PDK, Magic VLSI, netgen, surfer, iverilog, verilator)

Skywater 130 nm Tutorial

aicex

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Lower your expectations on EDA software

Expect that you will spend at least \(2\pi\) times more time than planned (mostly due to software issues)

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Questions

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Thanks!

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Summary

The real world is analog, so every IC carries analog circuits at its edges - there is no purely digital chip
Making an IC splits into an analog and a digital flow, and it is rare to find one human who does both well
Digital designers reuse each other's work; analog designers redraw - closing that gap is a theme of this course
What you need from here: the refresher chapters, a working toolchain, and the habit of simulating everything

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