VOLTAGE MODE BUCK

WHAT YOU ARE LOOKING AT

The PWM buck runs open loop: you set a duty cycle and the output lands wherever VDDH·D puts it. The notebook that page comes from ends by asking the obvious next question — "Can I make output voltage independent of input voltage? Yes. With a feedback loop." This page is that feedback loop.

Voltage mode means the only thing measured is the output voltage. The error against V_ref goes through a compensator, the compensator's output is compared against a sawtooth ramp, and that comparison makes the duty cycle. The awkward part is the plant. A buck's control-to-output response is

G_vd(s) = VDDH · Z(s) / (sL + R_s + Z(s)),   Z(s) = R(1 + sR_cC) / (1 + sC(R + R_c))

which has an LC double pole. Two poles close together means the phase falls through −180° in barely a decade, and it does so while the gain is still well above one. A single integrator on top of that is a loop that oscillates.

A type 3 compensator answers this with two zeros and three poles, one of them at the origin:

G_c(s) = A (1 + s/ω_z1)(1 + s/ω_z2) / [ s (1 + s/ω_p1)(1 + s/ω_p2) ]

The pole at the origin gives infinite DC gain, which is what makes the output independent of VDDH. The two zeros hand back up to 180° of phase around the crossover, which is what buys back what the LC took. The two remaining poles roll the gain off again before the switching frequency, so the loop does not amplify switching ripple. Here they are placed by the K-factor method, so the only things you choose are the crossover frequency and the phase margin.

The bottom row is the check. It runs the actual switching converter — comparator, ramp, both switches, the compensator integrated alongside — and steps first the input voltage and then the load. The averaged model in the top row is a prediction about what those transients will look like. Comparing the two is the entire point.

THINGS WORTH TRYING

• Tick open loop. The duty cycle freezes at whatever the loop had settled on, and the line step walks the output straight off to VDDH·D — a 40 % input change becomes a 40 % output change. Untick it and the same step barely dents the output. That is the DC gain of the integrator, and it is the whole reason for the loop.
• Pull the phase margin down to 30°. The closed loop peaks, the load step rings, and the number of cycles it rings for is exactly what the peaking predicts. Take it to 80° and the transient is clean but slow — and the compensator now needs so much boost that its poles have gone above the switching frequency, which is not something you can build.
• Compare crossover against slowest CL pole. On the defaults the loop crosses over at 50 kHz but the slowest closed-loop pole sits at 3.2 kHz, and it is that pole, not the crossover, that sets the long tail on both transients. The K-factor puts its two zeros a factor √K below the crossover, and a closed-loop pole follows them down. Crossover frequency and phase margin do not determine the transient — a thing worth knowing before promising someone a settling time.
• Push the crossover up and the tail does shorten, but not in proportion, for the reason above. Keep going and f_c approaches f_sw/2, where the design stops meaning anything: the averaged model is only valid well below the switching frequency, and you can watch switching ripple start to dominate the transient it is supposed to be correcting. A fifth to a tenth of f_sw is the usual rule and this is where it comes from.
• Raise the ESR from 5 mΩ to an ohm. The ESR zero walks down from megahertz into the loop, hands you phase for free, and the required boost drops — watch the readout. Less boost means a smaller K, which means the compensator zeros sit closer to the crossover, which pulls that slow closed-loop pole up with them and shortens the tail. This is why an old electrolytic output cap was easy to compensate and why swapping it for a ceramic broke the loop. Type 3 exists because ceramics have no ESR zero to lean on.
• Move L and C and watch f_LC and the required boost move together. The compensator is not designed against the components; it is designed against where the double pole lands.

THE MODEL

# Plant, averaged small signal, evaluated at s = j*2*pi*f
Z    = R*(1 + s*Resr*C) / (1 + s*C*(R + Resr))
G_vd = VDDH * Z / (s*L + Rs + Z)

# K-factor placement for a type 3
boost = PM - 90 - angle(G_vd(fc)/Vramp)
K     = tan(radians(boost/4 + 45))**2
fz1 = fz2 = fc/sqrt(K)
fp1 = fp2 = fc*sqrt(K)

# Time domain: the real switching loop, one dt at a time
e   = Vref - vo
vc  = compensator(e)                 # 3rd order state space, RK4
pmos = (ramp < vc)                   # ramp = (t mod T)/T
vx   = pmos*VDDH - Rs*iL
iL  += (vx - vo)/L * dt
vC  += (iL - vo/R)/C * dt
vo   = (vC + Resr*iL)/(1 + Resr/R)

This page has no notebook behind it — it is the loop jupyter/buck.ipynb describes in its closing markdown but never builds. The power stage integration is the notebook's, with the capacitor ESR added because a type 3 compensator's whole reason for existing is what happens when there is not enough of it. See the open-loop buck for the plant on its own, and the PFM buck for regulating the same stage with no linear loop at all.